1. Field of the Invention
The present invention relates to semiconductor chip packages, and more particularly to chip scale packages and tape for chip scale packages.
2. Description of the Related Art
In one exemplary assembly process, semiconductor chip packages are assembled through several processes. A semiconductor chip including a bonding pad is initially bonded on the surface of a die pad of a lead frame using an adhesive material. Inner leads of the lead frame are then electrically connected to the bonding pad of the semiconductor chip using a conductive wire. Thereafter, a portion including the semiconductor chip and the inner leads of the lead frame is encapsulated with a molding resin. The package is then subjected to a trimming and forming process and a plating process.
The conventional assembly process for semiconductor chip packages has a disadvantage in that the outer leads of the semiconductor chip package must be shaped for mounting on a printed circuit board (PCB). For example, the process forms the outer lead in a shape such as a gull wing shape or a J bend shape. Additionally, the package enclosing the semiconductor chip and a mounting member to be mounted on the PCB is larger than the semiconductor chip, and the outer leads of the semiconductor chip package are exposed. Accordingly, assembly of thinner and high density semiconductor chip packages is difficult.
Miniaturization of electronic equipments demands smaller semiconductor packages. However, a conventional plastic package, which includes a semiconductor chip and a lead frame in a molded body cannot be smaller than the semiconductor chip in the package. Further, the outer leads protruding from the molded body to be connected to a circuitboard make the conventional package even larger. To overcome the problems of conventional plastic packages, many kinds of new packages have been developed and introduced in electronic industry. Among them are a group of chip scale packages (CSPs), the sizes of which are almost the same as the semiconductor chips contained in the packages.
The structure of a conventional chip scale package will be briefly described hereinafter.
FIG. 1 is a top view of a patterned tape 10 which is bonded to the active surface of a semiconductor chip when forming a chip scale package. FIG. 2 is a schematic cross sectional view of a chip scale package including patterned tape 10.
As shown in FIG. 2, the chip scale package includes a semiconductor chip 1, a patterned tape 10, an adhesive layer 2 and solder balls 9. Patterned tape 10 is fabricated by laminating a copper film to a polyimide base film 6, and etching the copper film to form a pattern including beam leads 4, soldering pads 5 and conductor 7. In addition, as shown in FIG. 1, several windows (or slots) 8 in the patterned tape 10 allows bonding of beam leads 4 to chip bonding pads 3 of semiconductor chip 1. Beam leads 4 are typically plated with gold-nickel alloy. Polyimide base film 6 is also removed at soldering pads 5, where solder balls 9 attach. Solder balls 9 are tantamount to the outer leads of a conventional plastic package. The reference numeral 12 in FIG.1 represents an outline of the chip scale package, which is almost equivalent to the outline of semiconductor chip 1.
The manufacturing process of the chip scale package is briefly described hereinafter. First, patterned tape 10 is aligned above semiconductor chip 1, with each beam lead 4 being aligned over each corresponding chip bonding pad 3 of the semiconductor chip 1. After proper alignment, the patterned tape 10 is attached to the semiconductor chip 1 using an adhesive material 2 that includes an elastomer.
Thereafter, a heated capillary (not shown) presses each beam lead 4 from above to connect each beam lead 4 to a corresponding chip bonding pad. A sealing process applies sealing resin to the window of patterned tape 10 so that beam leads 4 and the active surface of semiconductor chip 1 exposed through windows 8 are encapsulated.
Then, solder balls 9 are positioned on soldering pads 5, and are connected to soldering pads 5 by a reflow process. Finally, patterned tape 10 is cut along line 12 to produce an individual chip scale package.
Beam leads 4, which connect to chip bonding pads 3 of semiconductor chip 1, are further described hereinafter.
FIG. 3 is a close-up view of portion A of FIG. 1. As shown in FIG.3, each beam lead 4 has a uniform width. Beam lead 4 exposed through the window 8 can be divided into three parts for the purpose of better understanding of the chip scale packages. The inner part of beam lead 4 which is close to conductor 7, the central part of beam lead 4, and the outer part of beam lead 4 which is close to the perimeter of the semiconductor chip are designated 4a, 4b and 4c, respectively.
In the bonding of each beam lead 4 to the corresponding chip bonding pad 3 pushes beam lead 4 downward. This applies mechanical stresses to beam leads 4. During this bonding process, outer part 4c of beam lead 4 must be disconnected to prevent any damage to the other parts of beam lead 4. However, when the width of beam lead 4 is uniform, the stresses are applied uniformly along the beam lead 4, and these stresses can severely damage cental part 4b and inner part 4a before outer part 4c is cut. Therefore, a method, that promotes the disconnection of outer part 4c of beam lead 4 without damaging the other parts of the beam lead 4 is desired.